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by DMV27
Tue Feb 27, 2007 4:39 am
Forum: Emulators
Topic: Tales of Phantasia...
Replies: 42
Views: 28310

Code: Select all

if (addr AND 0x800000) is not zero then
 return rom at (addr AND 0x3FFFFF)
else
 return rom at ((addr AND 0x1FFFFF) ADD 0x400000)
 (you can also use AND 0x3FFFFF if you do rom mirroring)

SRAM should be mapped to the standard HiROM SRAM region.
by DMV27
Thu Aug 17, 2006 9:51 pm
Forum: Development
Topic: 65816 Timing
Replies: 8
Views: 13923

Here is the GTE 65816 datasheet with the many corrections that I have added to it.

http://rapidshare.de/files/29783722/65c816.zip
by DMV27
Tue Jul 25, 2006 5:51 am
Forum: Development
Topic: Progress on reducing HQ2x to fit in L1 cache
Replies: 95
Views: 80336

And I still can't figure out why the frelling hell the code's not getting proper 64-bit RDTSC values. =-.-= It should not physically be possibly to get a negative result like it's turning out unless it's only doing the math in 32-bit mode for some reason, and I haven't been able to duplicate that s...
by DMV27
Mon Mar 13, 2006 12:10 pm
Forum: Development
Topic: Optimal RGB Mix/Clamped Add/Sub
Replies: 52
Views: 46728

This code can be used to average two colors. It does not need a carry bit, so it can be used with RGB565. avg = (x & y) + (((x ^ y) >> 1) & 0x7F7F7F7F); This code is exactly the same as the MMX op "paddusb". It can also be adjusted to work with field sizes other than 8-bits. ls = (...
by DMV27
Wed Oct 19, 2005 2:51 am
Forum: Development
Topic: Questions on enabling HDMA mid-frame
Replies: 13
Views: 11757

The only cause for concern was if writes to $420c cleared dotransfer, which they don't. The Energy Breaker map requires writes to $420C to clear the DoTransfer flag for a channel when that channel is disabled. My guess is that HDMA always runs on scanline zero, even if the DoTransfer flag is clear....
by DMV27
Tue Apr 05, 2005 10:33 pm
Forum: Development
Topic: Latch timing
Replies: 192
Views: 148741

anomie wrote:Ack, we lost the DMA timing info! I guess i'll have to rewrite it... Anything else we're missing?
I saved a copy of the thread before the forum went down. I'll re-post everything that was lost later tonight.
by DMV27
Sat Feb 05, 2005 4:05 pm
Forum: Development
Topic: Latch timing
Replies: 192
Views: 148741

Assume: m=0/x=1 { ldy #$00 : lda $20ff,y } -> This will *not* trigger cycle 3a. The first read does not cross the page boundary, and even though the second read does (reads from $2100), it doesn't count. This should be expected, given cycle 3a couldn't occur after cycle 4, but it's still weird. Why...
by DMV27
Fri Jan 28, 2005 9:40 am
Forum: Development
Topic: Latch timing
Replies: 192
Views: 148741

Which manual is this now? The manual is on the WDC website at the bottom right corner of the page ( Programmanual.pdf ). Why would CLI/SEI allow an IRQ but CLI/RTI not, due to pipelining? If an IRQ is pending and the I flag is set, then the instruction sequence CLI / SEI / NOP will cause an interru...
by DMV27
Thu Jan 27, 2005 7:55 pm
Forum: Development
Topic: Latch timing
Replies: 192
Views: 148741

I figured HDMA would wait until the current instruction had completed, like NMIs and IRQs. Probably... OTOH, i have a bit of a suspicion that for a "STA $420B ; NOP" the processor might just be paused for DMA after the opcode load but before the IO cycle, based on the open bus value. The ...

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