ZSNES board

Quite unusual is the fact that PPU1 has 2 address buses going to each 32k SRAM It's for interleaving data. Can help with multiple things, including mode 7. Hard to say, we know next to nothing about low-level PPU operation. You don't need 2 address buses for interleaving data. It most probably fetc...

I wouldn't wonder if a lot of ground/vcc pins being shown actually have a function. From anomie's register doc: 2133 wb+++- SETINI - Screen Mode/Video Select se--poIi s = "External Sync". Used for superimposing "sfx" graphics, whatever that means. Usually 0. Not much is known ab...

Quite unusual is the fact that PPU1 has 2 address buses going to each 32k SRAM, they probably did this so that in Mode 7, you could fetch 2 8bit pixels from seperate locations . Just to be sure: 2 address buses per 32K chip, or 1 address bus per chip? There are 2 * 32k SRAM chips, and each chip is ...

Continuing from this thread: http://board.zsnes.com/phpBB2/viewtopic.php?t=11230 The schematics reveal some interesting facts, which could be used to find out how the SNES works in detail. Both PPU's and the CPU are communicating via an 18bit data bus with each other. Why 18bit, and not 16? Since th...

The schematics reveal some interesting facts, which could be used to find out how the SNES works in detail. Bot PPU's are communicating via an 18bit data bus with each other. Quite unusual is the fact that PPU1 has 2 address buses going to each 32k SRAM, they probably did this so that in Mode 7, you...

Hi there, I was just wondering if PAL filter emulation is planned for further release. I mean, NTSC and PAL do not differ very much from each other (besides the 4,43 Mhz colour clock, YUV colour space and the phase alteration), so I presume the NTSC code could be modified to emulate the PAL colour a...